环境：ISE 10.1 语言：verilog HDL

出现的错误如下：

 ERROR:Xst:880 - "mst_pulse_calculation.v" line 124: Cannot mix blocking and non blocking assignments on signal <Res_in_div>.
ERROR:Xst:880 - "mst_pulse_calculation.v" line 125: Cannot mix blocking and non blocking assignments on signal <DiffCnt_in_div>.

看英文的意思是不能对信号同时进行阻塞和非阻塞赋值。

看一下程序，是这样的：

reg [31:0] Res_in_div;
reg [15:0] DiffCnt_in_div;
//assign Res_wire = Res_reg;
//assign DiffCntWire = MeasureDiffCnt;
always @ (posedge clk_200m)
 if(!rst)
  begin
   Res_in_div <= 0;
   DiffCnt_in_div <= 0;
  end
 else
  begin
   Res_in_div = Res_reg;
   DiffCnt_in_div = MeasureDiffCnt;
  end
注意一下红色加粗的部分，一个赋值时用的是阻塞赋值“<=”，而另一处用的是非阻塞赋值“=”，改正即可解决，一般我们都用阻塞赋值。